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Accel 34 Registers Settings
Settings for registers of Accel 34 Click driver. More...
Detailed Description
Settings for registers of Accel 34 Click driver.
Macro Definition Documentation
◆ ACCEL34_ACCEL_FSR_15G
| #define ACCEL34_ACCEL_FSR_15G 0 |
Accel 34 accel full scale range setting.
Specified setting for accel full scale range of Accel 34 Click driver.
◆ ACCEL34_ACCEL_FSR_30G
| #define ACCEL34_ACCEL_FSR_30G 1 |
◆ ACCEL34_ACCEL_FSR_60G
| #define ACCEL34_ACCEL_FSR_60G 2 |
◆ ACCEL34_DEVICE_ADDRESS_0
| #define ACCEL34_DEVICE_ADDRESS_0 0x1D |
Accel 34 device address setting.
Specified setting for device slave address selection of Accel 34 Click driver.
◆ ACCEL34_DEVICE_ADDRESS_1
| #define ACCEL34_DEVICE_ADDRESS_1 0x53 |
◆ ACCEL34_DEVICE_ADDRESS_2
| #define ACCEL34_DEVICE_ADDRESS_2 0x54 |
◆ ACCEL34_DEVICE_ADDRESS_3
| #define ACCEL34_DEVICE_ADDRESS_3 0x55 |
◆ ACCEL34_DEVID_AD
| #define ACCEL34_DEVID_AD 0xAD |
Accel 34 device ID setting.
Specified setting for device ID of Accel 34 Click driver.
◆ ACCEL34_DEVID_MST
| #define ACCEL34_DEVID_MST 0x1D |
◆ ACCEL34_DIG_EN_FIFO_EN_DIS
| #define ACCEL34_DIG_EN_FIFO_EN_DIS 0x00 |
◆ ACCEL34_DIG_EN_FIFO_EN_EN
| #define ACCEL34_DIG_EN_FIFO_EN_EN 0x08 |
◆ ACCEL34_DIG_EN_FIFO_EN_MASK
| #define ACCEL34_DIG_EN_FIFO_EN_MASK 0x08 |
◆ ACCEL34_DIG_EN_INT01_EVENT_EVENT
| #define ACCEL34_DIG_EN_INT01_EVENT_EVENT 0x02 |
◆ ACCEL34_DIG_EN_INT01_EVENT_LIVE
| #define ACCEL34_DIG_EN_INT01_EVENT_LIVE 0x00 |
◆ ACCEL34_DIG_EN_INT01_EVENT_MASK
| #define ACCEL34_DIG_EN_INT01_EVENT_MASK 0x02 |
◆ ACCEL34_DIG_EN_MODE_CHANNEL_EN_ALL
| #define ACCEL34_DIG_EN_MODE_CHANNEL_EN_ALL 0xF0 |
◆ ACCEL34_DIG_EN_MODE_CHANNEL_EN_MASK
| #define ACCEL34_DIG_EN_MODE_CHANNEL_EN_MASK 0xF0 |
◆ ACCEL34_DIG_EN_MODE_CHANNEL_EN_TEMP
| #define ACCEL34_DIG_EN_MODE_CHANNEL_EN_TEMP 0x80 |
◆ ACCEL34_DIG_EN_MODE_CHANNEL_EN_X
| #define ACCEL34_DIG_EN_MODE_CHANNEL_EN_X 0x10 |
Accel 34 DIG_EN register settings.
Specified DIG_EN register settings of Accel 34 Click driver.
◆ ACCEL34_DIG_EN_MODE_CHANNEL_EN_Y
| #define ACCEL34_DIG_EN_MODE_CHANNEL_EN_Y 0x20 |
◆ ACCEL34_DIG_EN_MODE_CHANNEL_EN_Z
| #define ACCEL34_DIG_EN_MODE_CHANNEL_EN_Z 0x40 |
◆ ACCEL34_DIG_EN_PARITY_EN_DIS
| #define ACCEL34_DIG_EN_PARITY_EN_DIS 0x00 |
◆ ACCEL34_DIG_EN_PARITY_EN_EN
| #define ACCEL34_DIG_EN_PARITY_EN_EN 0x01 |
◆ ACCEL34_DIG_EN_PARITY_EN_MASK
| #define ACCEL34_DIG_EN_PARITY_EN_MASK 0x01 |
◆ ACCEL34_INTX_MAP0_ACT
| #define ACCEL34_INTX_MAP0_ACT 0x20 |
◆ ACCEL34_INTX_MAP0_DATA_RDY
| #define ACCEL34_INTX_MAP0_DATA_RDY 0x01 |
◆ ACCEL34_INTX_MAP0_FIFO_FULL
| #define ACCEL34_INTX_MAP0_FIFO_FULL 0x02 |
◆ ACCEL34_INTX_MAP0_FIFO_OVERRUN
| #define ACCEL34_INTX_MAP0_FIFO_OVERRUN 0x04 |
◆ ACCEL34_INTX_MAP0_FIFO_WATERMARK
| #define ACCEL34_INTX_MAP0_FIFO_WATERMARK 0x08 |
◆ ACCEL34_INTX_MAP0_INACT
| #define ACCEL34_INTX_MAP0_INACT 0x40 |
◆ ACCEL34_INTX_MAP0_NVM_BUSY
| #define ACCEL34_INTX_MAP0_NVM_BUSY 0x80 |
Accel 34 INTx_MAPx registers settings.
Specified INTx_MAPx registers settings of Accel 34 Click driver.
◆ ACCEL34_INTX_MAP1_DOUBLE_TAP
| #define ACCEL34_INTX_MAP1_DOUBLE_TAP 0x02 |
◆ ACCEL34_INTX_MAP1_NVM_DONE
| #define ACCEL34_INTX_MAP1_NVM_DONE 0x80 |
◆ ACCEL34_INTX_MAP1_NVM_IRQ
| #define ACCEL34_INTX_MAP1_NVM_IRQ 0x40 |
◆ ACCEL34_INTX_MAP1_OVER_RANGE
| #define ACCEL34_INTX_MAP1_OVER_RANGE 0x10 |
◆ ACCEL34_INTX_MAP1_PARITY_ERR
| #define ACCEL34_INTX_MAP1_PARITY_ERR 0x08 |
◆ ACCEL34_INTX_MAP1_SINGLE_TAP
| #define ACCEL34_INTX_MAP1_SINGLE_TAP 0x01 |
◆ ACCEL34_INTX_MAP1_TRIPLE_TAP
| #define ACCEL34_INTX_MAP1_TRIPLE_TAP 0x04 |
◆ ACCEL34_INTX_MAP1_UV_FLAG
| #define ACCEL34_INTX_MAP1_UV_FLAG 0x20 |
◆ ACCEL34_OP_MODE_AUDIO_MODE_DIS
| #define ACCEL34_OP_MODE_AUDIO_MODE_DIS 0x00 |
◆ ACCEL34_OP_MODE_AUDIO_MODE_EN
| #define ACCEL34_OP_MODE_AUDIO_MODE_EN 0x10 |
◆ ACCEL34_OP_MODE_AUDIO_MODE_MASK
| #define ACCEL34_OP_MODE_AUDIO_MODE_MASK 0x10 |
◆ ACCEL34_OP_MODE_HEART_SOUND
| #define ACCEL34_OP_MODE_HEART_SOUND 0x01 |
◆ ACCEL34_OP_MODE_HP
| #define ACCEL34_OP_MODE_HP 0x0C |
◆ ACCEL34_OP_MODE_HP_ULP
| #define ACCEL34_OP_MODE_HP_ULP 0x0E |
◆ ACCEL34_OP_MODE_HP_VLP
| #define ACCEL34_OP_MODE_HP_VLP 0x0F |
◆ ACCEL34_OP_MODE_LP
| #define ACCEL34_OP_MODE_LP 0x04 |
◆ ACCEL34_OP_MODE_LP_ULP
| #define ACCEL34_OP_MODE_LP_ULP 0x06 |
◆ ACCEL34_OP_MODE_LP_VLP
| #define ACCEL34_OP_MODE_LP_VLP 0x07 |
◆ ACCEL34_OP_MODE_MASK
| #define ACCEL34_OP_MODE_MASK 0x0F |
◆ ACCEL34_OP_MODE_PDM_MODE_DIS
| #define ACCEL34_OP_MODE_PDM_MODE_DIS 0x00 |
◆ ACCEL34_OP_MODE_PDM_MODE_EN
| #define ACCEL34_OP_MODE_PDM_MODE_EN 0x20 |
◆ ACCEL34_OP_MODE_PDM_MODE_MASK
| #define ACCEL34_OP_MODE_PDM_MODE_MASK 0x20 |
◆ ACCEL34_OP_MODE_RANGE_15G
| #define ACCEL34_OP_MODE_RANGE_15G 0x00 |
Accel 34 OP_MODE register settings.
Specified OP_MODE register settings of Accel 34 Click driver.
◆ ACCEL34_OP_MODE_RANGE_30G
| #define ACCEL34_OP_MODE_RANGE_30G 0x40 |
◆ ACCEL34_OP_MODE_RANGE_60G
| #define ACCEL34_OP_MODE_RANGE_60G 0x80 |
◆ ACCEL34_OP_MODE_RANGE_MASK
| #define ACCEL34_OP_MODE_RANGE_MASK 0xC0 |
◆ ACCEL34_OP_MODE_RBW
| #define ACCEL34_OP_MODE_RBW 0x08 |
◆ ACCEL34_OP_MODE_RBW_ULP
| #define ACCEL34_OP_MODE_RBW_ULP 0x0A |
◆ ACCEL34_OP_MODE_RBW_VLP
| #define ACCEL34_OP_MODE_RBW_VLP 0x0B |
◆ ACCEL34_OP_MODE_STANDBY
| #define ACCEL34_OP_MODE_STANDBY 0x00 |
◆ ACCEL34_OP_MODE_ULP
| #define ACCEL34_OP_MODE_ULP 0x02 |
◆ ACCEL34_OP_MODE_VLP
| #define ACCEL34_OP_MODE_VLP 0x03 |
◆ ACCEL34_RESET
| #define ACCEL34_RESET 0x02 |
Accel 34 RESET register settings.
Specified RESET register settings of Accel 34 Click driver.
◆ ACCEL34_SCALE_FACTOR_LSB_PER_G
| #define ACCEL34_SCALE_FACTOR_LSB_PER_G 2000.0f |
Accel 34 data resolution settings.
Specified data resolution settings of Accel 34 Click driver.
◆ ACCEL34_STATUS3_DATA_READY
| #define ACCEL34_STATUS3_DATA_READY 0x01 |
Accel 34 STATUS3 register settings.
Specified STATUS3 register settings of Accel 34 Click driver.
◆ ACCEL34_TEMP_OFFSET_LSB
| #define ACCEL34_TEMP_OFFSET_LSB 295 |
◆ ACCEL34_TEMP_SENS
| #define ACCEL34_TEMP_SENS 10.2f |
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